제목 : Large-Area Electronics based on Vertically Stacked Heterostructures

내용 :  We demonstrate a new device architecture for flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–semiconductor–metal heterostructures and ion gel gate dielectrics. The vertical SB transistor structure was formed by (i) vertically sandwiching a semiconductor layer between graphene (source) and metal (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with the vertical channel through an ion gel. Various kinds of semiconductors such as transition mechanically-exfoliated metal dicharcogenides(MoS2 and WSe2), vacuum-deposited organic semiconductors (pentacene and PTCDI-C8), solution-processed indium-gallium-zinc-oxides, and polymer semiconductors were successfully applied as a vertical channel materials. The channel current was controlled by adjusting the SB height at the graphene/semiconductor heterojunction under application of an external gate voltage. The high intrinsic capacitance of the ion-gel gate dielectric facilitated modulation of the SB height at the source/channel heterojunction to around 0.5 eV at a gate voltage lower than 2 V. The resulting vertical SB transistors exhibited a high current density, a high on−off current ratio, and excellent operational and environmental stabilities. The simple structure of the unit transistor enables the successful fabrication of low-power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large-area, and room-temperature deposition of both semiconductors and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene-based future electronics.