▷ 제목: Materials Research at SAIT for Disruptive Semiconductor Devices

▷ 내용: In this presentation, I aim to introduce the material research conducted at SAIT, focusing on its direct implication to disruptive semiconductor devices. Firstly, as we confront the limitations posed by the lateral scaling in three prominent product categories: Logic, DRAM, and Flash, our efforts are dedicated to the development of innovative materials capable of surpassing these constraints, thereby shaping the trajectory of future advancements. The overarching motif underpinning our material research for these revolutionary devices centers around the concept of three-dimensional integration for individual components, coupled with their hetero-integration, aimed at enhanced performance and minimal energy consumption. To achieve the 3D scheme, several ongoing projects are focused on various materials spanning from high-k dielectric to oxide semiconductors and metal interconnects. Specifically, I will discuss our recent progress in comprehending the fundamentals of ferroelectric materials for logic and memory applications.

Given the escalating power density, which results in inevitable heat dissipation in logic devices, we demonstrate that leveraging the negative differential capacitance of ferroelectric hafnia in ultrathin limit in the gate stack of a logic transistor has the potential to reduce power consumption by 30%. This reduction is achieved through gate capacitance enhancement. We propose the incorporation of ferroelectric material as a fundamental solution to address the thermal challenge, thereby playing a pivotal role in the architecture of 3D stack FETs.

As one of the candidates for 3D DRAM and ultimate vertical NAND, I will present a three-terminal ferroelectric FET that shows an unprecedented sub-ns switching speed. This feature makes it applicable to vertical DRAM as well as advanced VNAND. Due to efficient polarization switching replacing high-voltage charge tunneling, a ferroelectric FET that utilizes lower voltage to store multi-bit information within a cell enables vertical scaling of a cell in vertical NAND.